PIN diodes for photodetection and high-speed, high-resolution image sensing

ABSTRACT

The present invention provides high-speed, high-efficiency PIN diodes for use in photodetector and CMOS imagers. The PIN diodes include a layer of intrinsic semiconducting material, such as intrinsic Ge or intrinsic GeSi, disposed between two tunneling barrier layers of silicon oxide. The two tunneling barrier layers are themselves disposed between a layer of n-type silicon and a layer of p-type silicon.

STATEMENT OF GOVERNMENT RIGHTS

Research funding was provided for this invention by the National ScienceFoundation under Grant No. 0079983. The United States government hascertain rights in this invention.

FIELD OF THE INVENTION

This invention relates to PIN diodes for use in photodetectors and CMOSoptical imagers.

BACKGROUND

Multispectral photon detection (covering the visible and infrared)allows target identification with enhanced information content. Forexample, in military applications, multispectral-photodetector arrayscan be used to identify real missile heads from fake ones and can helpdirect the antimissile head toward an actual target. The principle ofmultispectral detection has been widely used in astronomic observations.One available photodetection mechanism is electron-hole generation in areverse-biased PIN diode

For PIN diode-based photodetectors, the longest wavelength that can bedetected is dictated by the bandgap of the intrinsic semiconductor usedfor the intrinsic layer. Photons with energy higher than the bandgapenergy will be detected, as long as the intrinsic layer is sufficientlythick to absorb the photons. The photodetectors must provide highefficiency and high-speed operation in order to use them for high-speedobject detection. To integrate photodetectors on a CMOS chip, where highspeed and sophisticated digital signal processing circuitry can be made,Group IV-based detectors may be desirable. The current approaches ofmaking photodetectors on a Si chip generally employ thick Si PIN diodesthat are vertically buried deep in the Si substrate. For these PIN diodephotodetectors, efficiency can be kept high as long as the intrinsiclayer is thick enough. However, the speed of these PIN diodes is ratherlow, because of the long tail of collection of photon current (due tothe low drift velocity of holes).

Ge is a promising material for light detection in optical communicationfor at least two reasons. First, because of its direct bandgap at 0.8 eVand indirect bandgap of 0.66 eV, it is highly absorbing over a widerange. Second, because of its compatibility with existing Si technology,it offers the potential for high-quality CMOS compatible integratedphotoreceivers. Unfortunately, due to the large lattice mismatch betweenSi and Ge, progress toward the formation of Ge-based high-speedphotodetectors on Si has been very limited.

Some work has been done to fabricate photodetectors using growth of Gequantum dots on Si surfaces to make many alternating layers of Si filmand Ge quantum dots. Although such photodetectors provide some increasein absorption, they show only a slight improvement over Si PIN diodes.

SUMMARY OF THE INVENTION

The present invention provides high-speed, high-efficiency PIN diodesfor use as photodetector, and in CMOS imagers. The PIN diodes include alayer of intrinsic semiconducting material disposed between twotunneling barrier layers of silicon oxide. The two tunneling barrierlayers are themselves disposed between a layer of n-type silicon and alayer of p-type silicon.

In a preferred embodiment, the intrinsic semiconducting material is asingle-crystal germanium (Ge) nanomembrane or GeSi alloy nanomembraneand the p- and n-type silicon (Si) layers are single-crystal Sinanomembranes. The Ge or GeSi nanomembranes desirably have a thicknessof no more than about 2,000 nm (the thickness depends on the tradeoffbetween speed and efficiency of photodetectors) and are separated bysilicon oxide layers desirably having a thickness of no more than about10 nm to provide a nanomembrane stack.

The nanomembrane stacks may be made by transferring the thin intrinsicGe or GeSi layer onto a thin silicon layer having a very thin oxidelayer on its surface. A second thin silicon layer (having a differentdoping type than the first) with a thin oxide layer on its surface maythen be transferred onto the single-crystal Ge or GeSi layer.Alternatively, the second oxide layer may be formed on the Ge or GeSilayer by growing and oxidizing a thin layer of Si prior to the transferof a second thin silicon layer onto the stack. In one embodiment, the Genanomembrane is the top device layer of a Ge-on-insulator substratewhich has been released by etching away an underlying sacrificial layer(e.g., a buried oxide layer). In another embodiment, some amount of Sican be incorporated into a Ge device layer of a Ge-on-insulatorsubstrate to form a GeSi alloy layer, which is subsequently released byetching away the underlying sacrificial layer. The released intrinsicGeSi or Ge nanomembrane may be transferred directly onto the oxidizeddevice layer of a Si-on-insulator substrate. Alternatively, the releasednanomembrane may be lifted and transferred using a host substrate.

A voltage source connected to electrodes that are electrically coupledto the n- and p-type silicon layers may be used to provide a reversebias across the PIN diode, allowing the PIN diode to act as aphotodetector. A plurality of such photodetectors may be arranged in anarray to provide a photodetector array. A CMOS circuit coupled to thephotodetector array may be used to provide a CMOS image sensor.

Further objects, features and advantages of the invention will beapparent from the following detailed description when taken inconjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a wavelength-specific photodetectorin accordance with the present invention.

FIG. 2 is an illustrative layout for a multispectral photodetector arrayin accordance with the present invention.

FIG. 3 is a schematic diagram showing a top view of the photodetector ofFIG. 1.

FIG. 4 is a schematic diagram showing a method for making aphotodetector in accordance with the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention provides PIN diodes with structures that improveboth the speed and efficiency of photodetectors that incorporate the PINdiodes. Photodetectors made from the PIN diodes can be easily integratedwith silicon processing techniques and CMOS-based devices, such asdigital imagers.

As illustrated in FIG. 1, the PIN diodes include an n-type silicon layer100; a first tunneling barrier layer 102 comprising silicon oxidedisposed above the n-type silicon layer; a layer of intrinsicsemiconducting material 104 disposed above the first tunneling barrierlayer; a second tunneling barrier layer 106 comprising silicon oxidedisposed above the layer of intrinsic semiconducting material; and ap-type silicon layer 108 disposed above the second tunneling barrierlayer. In a typical embodiment, each of the aforementioned layers isdisposed above and in direct contact with its preceding layer.

The PIN diodes may also include a first electrode 110 electricallycoupled to the n-type silicon layer and a second electrode 112electrically coupled to the p-type silicon layer. When a voltage sourceis connected to the first and second electrodes and a reverse bias isapplied across the PIN diode, the PIN diode acts as a photodetector,wherein photons absorbed in the intrinsic layer generate charge carriers(i.e., electrons and holes) that are collected at their respectiveelectrodes to generate a photocurrent. When charge carriers are createdin the intrinsic layer by photons of different energies, these chargecarriers will also have a range of energies. The silicon oxide tunnelingbarrier layers have a conduction band energy that is higher than theconduction band energy of the intrinsic semiconductor material andvalance band energy that is lower than the valence band energy of theintrinsic semiconductor material. Energy barriers will be present forthe charge carriers. However, the thickness of the silicon oxide on bothsides is very thin. Based on quantum physics, the wave function ofcharge carriers with sufficient kinetic energy will overlap with thethin energy barriers. Due to the overlapping of the wave function,charge carriers can be found on the other side of the oxide energybarrier. This phenomenon is well known as tunneling. Higher-energycarriers will have higher probability across the thin energy barriers.Therefore, the tunneling barrier layers allow only those electrons andholes with sufficiently high energy to tunnel through the barrier and becollected by the electrodes. By selecting those carriers having higherenergies (the tunneling barriers act like an high-energy-pass filter forcharge carriers), the use of tunneling barrier layers improves the speedof the photodetectors.

While the speed of the photodetectors is improved with the introductionof the tunneling barrier layers, the photocurrent collection efficiencywill inevitably be sacrificed, as only the “fast” electrons and holeswill be collected. For this reason, a Ge or GeSi intrinsic layer isadvantageous because it increases (typically, by several orders,relative to silicon) the absorption efficiency of photons, improving theefficiency of photocurrent generation, and therefore the sensitivity ofthe photodetector. Ge is known to have a much higher efficiency forabsorbing photons, over a wider range of wavelengths than Si. Theintrinsic semiconducting material desirably comprises intrinsic Ge,desirably in the form of a thin, continuous, single-crystalnanomembrane.

In a preferred embodiment, the intrinsic layer has a thickness of nomore than about 2000 nm. This includes embodiments where the intrinsiclayer has a thickness of no more than about 1000 nm, further includesembodiments where the intrinsic layer has a thickness of no more thanabout 500 nm and still further includes embodiments where the intrinsiclayer has a thickness of no more than about 200 nm. The n- and p-typesilicon layers are also desirably quite thin. In some embodiments thesilicon layers have a thickness of no more than about 1000 nm. Thisincludes embodiments where the silicon layers have a thickness of nomore than about 500 nm and further includes embodiments where thesilicon layers have a thickness of no more than about 200 nm. Thesilicon oxide layers separating the n- and p-type silicon layers fromthe intrinsic layer typically have a thickness of no more than about 10nm. This includes embodiments where the silicon oxide layers have athickness of no more than about 5 nm and further includes embodimentswhere the silicon oxide layers have a thickness of no more than about 2nm.

As illustrated in FIG. 2, a plurality of the photodetectors 200 may bearranged in an array to provide a photodetector array and CMOS circuitrymay be coupled to the photodetector array to provide a CMOS imagesensor. To achieve multispectral detection, one or more filters 202 fordifferent wavelengths may be disposed over one or more different areasof a photodetector array. However, the use of filters is optional. Thesefilters are widely available and can be easily implemented in theproposed photodetector arrays. The digital imaging information obtainedfrom different areas may be processed together using CMOS digitalcircuitry. The CMOS circuit for image processing may be fabricated on asubstrate (e.g., a silicon substrate) underlying the PIN diodes or onthe n- and p-type Si layers. Photodetector arrays composed of PIN diodesand CMOS circuits for use with photodetector arrays are known.Descriptions of appropriate layouts for arrays of PIN diodes and CMOScircuits for use with arrays of PIN diodes are described in U.S. Pat.Nos. 6,809,358 and 6,831,263; the entire disclosures of which areincorporated herein by reference.

FIG. 3 shows a top view of a single pixel in a CMOS image sensor thatincludes the PIN diode of FIG. 1 and CMOS circuitry 300. In theembodiment of FIG. 3, a layer of insulation 302 is disposed around thepin diode and the perimeter of the pixel.

FIG. 4 shows an example of a fabrication process flow that may be usedto make high-speed and high-efficiency CMOS compatible photodetectors inaccordance with the present invention. In this illustrative process, Siand Ge nanomembranes are employed. The base substrate upon which the PINdiode is fabricated is a Si-on-insulator substrate 400 that includes athin, n-type silicon layer 402 over a buried oxide layer 404 that issupported on a silicon handle layer 406. (See step (a).) Silicon layer402 has a thin oxide layer 408 on its surface. (See step (b).) Oxidelayer 408 may be a native oxide layer or may be generated by a separateoxidation process. Silicon layer 402 does not have to be the templatelayer of a silicon-on-insulator wafer, as in FIG. 4. Instead, siliconlayer 402 and its oxide layer 408 may be pre-fabricated and transferredfrom a separate substrate. A single-crystal intrinsic Ge layer 410,which has been released from a Ge-on-insulator substrate by removing asacrificial layer under the Ge layer, is transferred and bonded tosilicon oxide layer 408. Ge layer 410 may be transferred with apre-grown Si layer 412 which is subsequently oxidized to provide asilicon oxide layer 414. (See steps (c) and (d).) A p-type silicon layer416 is then transferred and bonded to silicon oxide layer 414. (See step(e).) A mesa 418 is then etched into layers 410, 414 and 416 andelectrodes 420 are deposited on n-type silicon layer 402 and p-typesilicon layer 416. (See step (f).) As shown in FIGS. 1 and 3, theelectrode on the p-type silicon layer may define a central opening forthe light to go through. The electrode formation may be done aftersurface passivation using PECVD oxide or grown oxide or nitride. Viaholes for metal contacts may be desirable if passivation is used. Thepositions of p-type and n-type silicon can be exchanged.

In some embodiments, as shown, for example, in FIGS. 1 and 4, the PINdiodes are fabricated on a solid semiconductor-on-insulator support.However, in other embodiments, the nanomembrane stack can be transferredto a flexible substrate (e.g., a plastic film), to provide flexiblephotodetectors and imagers and to allow light coupled from the backsideof the PIN diodes. If a spherically formed flexible substrate is used,an artificial eye or similar device can be made.

The nanomembrane transfer process of steps (c) and (e) in FIG. 4 may becarried out as follows. The intrinsic layer may be fabricated from adevice substrate that includes a thin layer of single-crystal Ge or GeSisupported on a sacrificial layer (e.g., a buried oxide layer). Theintrinsic layer is then released from the sacrificial layer by removing(e.g., etching) the sacrificial layer, lifting the released layer andtransferring the released layer. Lifting the released layer may becarried out by contacting the released layer with a host substrate or atape which can be vaporized upon low-temperature heating after finishingtransfer, to which the upper surface of the released layer adheres. Insome embodiments, the host substrate itself forms part of the PIN diode.For example, the host substrate may be an n- or p-doped silicon layerwith a native oxide on its surface. In other embodiments, the hostsubstrate provides a temporary support on which the released layer istransported before being transferred to an n- or p-doped silicon layerwith a native oxide on its surface. A similar process may be used toform and transfer a released n- or p-type silicon layer. The hostsubstrate is generally characterized by at least one surface to whichthe released layer adheres. Generally, the host substrate will be coatedwith an adhesive coating to promote adhesion of the released layer.

For the purposes of this disclosure and unless otherwise specified, “a”or “an” means “one or more”. All patents, applications, references andpublications cited herein are incorporated by reference in theirentirety to the same extent as if they were individually incorporated byreference.

While the principles of this invention have been described in connectionwith specific embodiments, it should be understood clearly that thesedescriptions are made only by way of example and are not intended tolimit the scope of the invention.

1. A PIN diode comprising: (a) a layer of n-type silicon; (b) a firsttunneling barrier layer of silicon dioxide disposed over the layer ofn-type silicon; (c) no more than a single layer of single-crystalintrinsic semiconducting material disposed over the first tunnelingbarrier layer; (d) a second tunneling barrier layer of silicon dioxidedisposed over the layer of single-crystal intrinsic semiconductingmaterial; and (e) a layer of p-type silicon disposed over the secondtunneling barrier layer, wherein the first and second tunneling barrierlayers are each continuous silicon dioxide layers.
 2. The PIN diode ofclaim 1, further comprising a first electrode electrically coupled tothe layer of n-type silicon and a second electrode electrically coupledto the layer of p-type silicon.
 3. The PIN diode of claim 2, wherein avoltage source is connected to the first and second electrodes toprovide a photodetector.
 4. The PIN diode of claim 1, wherein the layerof single-crystal intrinsic semiconducting material has a thickness ofno more than about 2000 nm.
 5. The PIN diode of claim 1, wherein thelayer of single-crystal intrinsic semiconducting material has athickness of no more than about 200 nm.
 6. The PIN diode of claim 1,wherein the layer of single-crystal intrinsic semiconducting material isa single-crystal layer of intrinsic germanium.
 7. The PIN diode of claim6, wherein the layer of single-crystal intrinsic germanium has athickness of no more than about 1000 nm.
 8. The PIN diode of claim 6,wherein the layer of single-crystal intrinsic germanium has a thicknessof no more than about 500 nm.
 9. The PIN diode of claim 6, wherein thelayer of n-type silicon and the layer of p-type silicon aresingle-crystal layers with thicknesses of no more than about 1000 nm.10. The PIN diode of claim 6, wherein the layer of n-type silicon andthe layer of p-type silicon are single-crystal layers with thicknessesof no more than about 500 nm.
 11. The PIN diode of claim 7, wherein thefirst and second tunneling barrier layers have a thickness of no morethan about 10 nm.
 12. The PIN diode of claim 1, wherein the layer ofsingle-crystal intrinsic semiconducting material is a layer ofsingle-crystal intrinsic germanium-silicon alloy.
 13. The PIN diode ofclaim 12, wherein the layer of single-crystal intrinsicgermanium-silicon alloy has a thickness of no more than about 2000 nm.14. The PIN diode of claim 12, wherein the layer of n-type silicon andthe layer of p-type silicon are single-crystal layers with thicknessesof no more than about 1000 nm.
 15. The PIN diode of claim 14, whereinthe first and second tunneling barrier layers have a thickness of nomore than about 10 nm.
 16. A photodetector array comprising a pluralityof PIN diodes according to claim 3, arranged in an array.
 17. Thephotodetector array of claim 16, further comprising at least one opticalfilter disposed over one or more of the plurality of PIN diodes.
 18. Animage sensor comprising the photodetector array of claim 16 and furthercomprising a CMOS circuit coupled to the photodetector array.
 19. A PINdiode comprising: (a) a layer of n-type silicon having a thickness of nomore than about 1000 nm; (b) a first tunneling barrier layer of silicondioxide disposed over the layer of n-type silicon; (c) no more than asingle layer of single-crystal intrinsic germanium having a thickness ofno more than about 2000 nm disposed over the first tunneling barrierlayer; (d) a second tunneling barrier layer of silicon dioxide disposedover the layer of single-crystal intrinsic germanium; and (e) a layer ofp-type silicon having a thickness of no more than about 1000 nm disposedover the second tunneling barrier layer, wherein the first and secondtunneling barrier layers are each continuous silicon dioxide lavers. 20.The PIN diode of claim 19, wherein the layers of n-type and p-typesilicon have thicknesses of no more than about 500 nm and the layer ofsingle-crystal intrinsic germanium has a thickness of no more than about200 nm.
 21. The PIN diode of claim 19, wherein a first electrode iselectrically coupled to the layer of n-type silicon and a secondelectrode is electrically coupled to the layer of p-type silicon and avoltage source is connected to the first and second electrodes toprovide a photodetector.
 22. A photodetector array comprising aplurality of PIN diodes according to claim 21, arranged in an array. 23.The photodetector array of claim 22, further comprising at least oneoptical filter disposed over one or more of the plurality of PIN diodes.24. An image sensor comprising the photodetector array of claim 22 andfurther comprising a CMOS circuit coupled to the photodetector array.25. A PIN diode comprising: (a) a layer of n-type silicon having athickness of no more than about 1000 nm; (b) a first tunneling barrierlayer of silicon dioxide disposed over the layer of n-type silicon; (c)no more than a single layer of single-crystal intrinsicgermanium-silicon alloy having a thickness of no more than about 2000 nmdisposed over the first-tunneling barrier layer; (d) a second tunnelingbarrier layer of silicon dioxide disposed over the layer ofsingle-crystal intrinsic germanium-silicon alloy; and (e) a layer ofp-type silicon having a thickness of no more than about 1000 nm disposedover the second tunneling barrier layer, wherein the first and secondtunneling barrier layers are each continuous silicon dioxide layers. 26.The PIN diode of claim 25, wherein the layers of n-type and p-typesilicon have thicknesses of no more than about 500 nm and the layer ofsingle-crystal intrinsic germanium-silicon alloy has a thickness of nomore than about 200 nm.
 27. The PIN diode of claim 25, wherein a firstelectrode is electrically coupled to the layer of n-type silicon and asecond electrode is electrically coupled to the layer of p-type siliconand a voltage source is connected to the first and second electrodes toprovide a photodetector.
 28. A photodetector array comprising aplurality of PIN diodes according to claim 27, arranged in an array. 29.The photodetector array of claim 28, further comprising at least oneoptical filter disposed over one or more of the plurality of PIN diodes.30. An image sensor comprising the photodetector array of claim 28 andfurther comprising a CMOS circuit coupled to the photodetector array.31. A PIN diode comprising: (a) a layer of n-type silicon; (b) a firsttunneling barrier layer of silicon dioxide disposed over the layer ofn-type silicon; (c) a layer of single-crystal intrinsic semiconductingmaterial disposed over the first tunneling barrier layer; (d) a secondtunneling barrier layer of silicon dioxide disposed over the layer ofsingle-crystal intrinsic semiconducting material; and (e) a layer ofp-type silicon disposed over the second tunneling barrier layer, whereinthe layer of single-crystal intrinsic semiconducting materialsubstantially spans the length of the layer of p-type silicon, furtherwherein the layer of single-crystal intrinsic semiconducting material isin direct contact with the first tunneling barrier layer, the secondtunneling barrier layer, or both, and further wherein the first andsecond tunneling barrier layers are each continuous silicon dioxidelayers.
 32. The PIN diode of claim 31, wherein the layer of n-typesilicon and the layer of p-type silicon each have a thickness of no morethan about 1000 nm, and further wherein the single layer ofsingle-crystal intrinsic semiconducting material is a single layer ofsingle-crystal intrinsic germanium having a thickness of no more thanabout 2000 nm.
 33. The PIN diode of claim 31, wherein the layer ofn-type silicon and the layer of p-type silicon each have a thickness ofno more than about 1000 nm, and further wherein the single layer ofsingle-crystal intrinsic semiconducting material is a single layer ofsingle-crystal intrinsic germanium-silicon alloy having a thickness ofno more than about 2000 nm.
 34. A PIN diode comprising: (a) a layer ofn-type silicon; (b) a first tunneling barrier layer of silicon dioxidedisposed over the layer of n-type silicon; (c) a layer of single-crystalintrinsic semiconducting material disposed over the first tunnelingbarrier layer; (d) a second tunneling barrier layer of silicon dioxidedisposed over the layer of single-crystal intrinsic semiconductingmaterial; and (e) a layer of p-type silicon disposed over the secondtunneling barrier layer; wherein the layer of single-crystal intrinsicsemiconducting material runs along an axis running parallel to andbetween the first tunneling barrier layer and the second tunnelingbarrier layer, further wherein there is no more than a single layer ofthe single-crystal intrinsic semiconducting material running along theaxis between the first tunneling barrier layer and the second tunnelingbarrier layer, and further wherein the first and second tunnelingbarrier layers are each continuous silicon dioxide layers.
 35. The PINdiode of claim 34, wherein the layer of single-crystal intrinsicsemiconducting material is in direct contact with the first tunnelingbarrier layer, the second tunneling barrier layer, or both.
 36. The PINdiode of claim 1, wherein the layer of single-crystal intrinsicsemiconducting material is in direct contact with the first tunnelingbarrier layer, the second tunneling barrier layer, or both.
 37. The PINdiode of claim 19, wherein the layer of single-crystal intrinsicgermanium is in direct contact with the first tunneling barrier layer,the second tunneling barrier layer, or both.
 38. The PIN diode of claim25, wherein the layer of single-crystal intrinsic germanium-siliconalloy is in direct contact with the first tunneling barrier layer, thesecond tunneling barrier layer, or both.